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1/16 ? semiconductor msm512100/l description the msm512100/l is a 2,097,152-word 1-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm512100/l achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/single-layer metal cmos process. the msm512100/l is available in a 26/20-pin plastic soj. the msm512100l (the low-power version) is specially designed for lower-power applications. features ? 2,097,152-word 1-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (l-version) ? fast page mode, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? multi-bit test mode capability ? package: 26/20-pin 300 mil plastic soj (soj26/20-p-300-1.27) (product : msm512100/l-xxsj) xx indicates speed rank. product family ? semiconductor msm512100/l 2,097,152-word 1-bit dynamic ram : fast page mode type msm512100/l-70 70 ns 130 ns 150 ns 385 mw 330 mw 5.5 mw/ family access time (max.) cycle time (min.) standby (max.) power dissipation msm512100/l-80 t rac 80 ns 35 ns t aa 40 ns 20 ns t cac 20 ns msm512100/l-60 60 ns 110 ns 440 mw 30 ns 15 ns operating (max.) 0.55 mw (l-version) 20 ns t oea 20 ns 15 ns e2g0016-17-41 this version: jan. 1998 previous version: may 1997
2/16 ? semiconductor msm512100/l pin configuration (top view) 3 4 5 9 10 11 12 13 ras nc a10r a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 cas oe a9 a8 a7 a6 a5 a4 2 we 25 d out 1 d in 26 v ss 26/20-pin plastic soj pin name function a0 - a9, a10r address input ras row address strobe cas column address strobe d in data input d out data output we write enable v cc power supply (5 v) v ss ground (0 v) nc no connection oe output enable
3/16 ? semiconductor msm512100/l block diagram we timing generator timing generator column decoders write clock generator sense amplifiers i/o selector output buffer d out d in input buffer memory cells row address buffers on chip v bb generator v cc v ss internal address counter column address buffers refresh control clock a0 - a9 ras cas row de- coders word drivers 10 11 10 10 1 a10r oe
4/16 ? semiconductor msm512100/l electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C1.0 min. 5.5 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a9, a10r, d in ) input capacitance ( ras , cas , we , oe ) output capacitance (d out ) c in1 symbol c in2 c out 6 7 7 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ.
5/16 ? semiconductor msm512100/l dc characteristics parameter symbol condition msm512100 /l-60 msm512100 /l-70 msm512100 /l-80 (v cc = 5 v 10%, ta = 0c to 70c) i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v d out disable output leakage current 0 v v o 5.5 v ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) d out = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t pc = min. (fast page mode) t rc = 125 m s, average power v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 i cc10 cas before ras , supply current t ras 1 m s (battery backup) 3 v cc C0.2 v min. 2.4 0 C10 C10 max. v cc 0.4 10 10 80 2 1 80 5 80 60 200 100 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 70 2 1 70 5 70 50 200 100 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 60 2 1 60 5 60 40 200 100 unit v v m a m a ma ma ma ma ma ma m a m a note 1, 2 1 1, 2 1 1, 2 1, 3 1, 4, 5 1, 5 ras cycling, notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih . 4. v cc C 0.2 v v ih 6.5 v, C1.0 v v il 0.2 v. 5. l-version.
6/16 ? semiconductor msm512100/l ac characteristics (1/2) parameter random read or write cycle time (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 11, 12 msm512100 /l-60 read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address output low impedance time from cas transition time refresh period refresh period (l-version) ras precharge time ras pulse width (fast page mode) ras hold time cas precharge time (fast page mode) cas pulse width ras pulse width cas hold time cas to ras precharge time ras to cas delay time ras to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from cas precharge note 4, 5, 6 4, 5 4, 6 7 3 5 6 4 4 ras hold time from cas precharge cas to data output buffer turn-off delay time symbol t rc t rwc t pc t prwc t rac t cac t aa t clz t off t t t ref t ref t rp t ras t rasp t rsh t cp t cas t csh t crp t rcd t rad t asr t rah t asc t cah t ar t ral t cpa t rhcp min. 110 130 40 60 0 0 3 40 60 60 15 10 15 60 5 20 15 0 10 0 15 50 30 35 max. 60 15 30 15 50 16 128 10,000 100,000 10,000 45 30 35 unit ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 130 155 45 70 0 0 3 50 70 70 20 10 20 70 5 20 15 0 10 0 15 55 35 40 max. 70 20 35 20 50 16 128 10,000 100,000 10,000 50 35 40 max. 80 20 40 20 50 16 128 10,000 100,000 10,000 60 40 45 min. 150 175 50 75 0 0 3 60 80 80 20 10 20 80 5 20 15 0 10 0 15 60 40 45 msm512100 /l-70 msm512100 /l-80 access time from oe 4 t oea 15 ns 20 20 7 oe to data output buffer turn-off delay time t oez 015 ns 020 20 0 15 ns 20 20 ras hold time referenced to oe t roh
7/16 ? semiconductor msm512100/l ac characteristics (2/2) symbol parameter read command set-up time t rcs read command hold time t rch msm512100 /l-60 read command hold time referenced to ras write command set-up time write command hold time write command hold time from ras write command pulse width write command to ras lead time write command to cas lead time data-in set-up time t rrh t wcs t wch t wcr t wp t rwl t cwl t ds data-in hold time t dh data-in hold time from ras t dhr cas to we delay time t cwd column address to we delay time t awd ras to we delay time cas active delay time from ras precharge ras to cas set-up time ( cas before ras ) ras to cas hold time ( cas before ras ) we to ras precharge time ( cas before ras ) we hold time from ras ( cas before ras ) ras to we set-up time (test mode) ras to we hold time (test mode) t rwd t rpc t csr t chr t wrp t wrh t wts t wth (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 11, 12 cas precharge we delay time t cpwd unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 0 0 0 0 10 45 10 15 15 0 15 50 15 30 60 5 5 10 10 10 10 10 35 max. min. 0 0 0 0 10 50 10 20 20 0 15 55 20 35 70 5 5 10 10 10 10 10 40 max. min. 0 0 0 0 10 60 10 20 20 0 15 60 20 40 80 5 5 10 10 10 10 10 45 max. msm512100 /l-70 msm512100 /l-80 note 8 8 9 9 9 9 9 10 10 oe command hold time t oeh ns 15 20 20 oe to data-in delay time t oed ns 15 20 20
8/16 ? semiconductor msm512100/l notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 100 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 11. the test mode is initiated by performing a we and cas before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is generated. the test mode specified in this data sheet is a 4-bit parallel test function. ra10 and ca0 are not used. in a read cycle, if all internal bits are equal, the data output pin will indicate a high level. if any internal bits are not equal, the data output pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operating state by performing a ras -only refresh cycle or a cas before ras refresh cycle. 12. in a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. these parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
9/16 ? semiconductor msm512100/l ras cas address we d out v ih v il C C v ih v il e e v ih v il e e v ih v il e e v oh v ol e e t rc t ras t rp t csh t crp t rcd t rsh t crp t cas t rad t ral t asr t rah t asc t cah row column t ar t rcs t rch t rrh t cac t aa t clz t rac t off open valid data "h" or "l" oe v ih v il C C t roh t oea t oez timing waveform read cycle write cycle (early write) ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rc t ras t rp t csh t crp t rcd t rsh t crp t cas t ar t rad t ral t rah t asr t asc t cah row column t cwl t wcr t wcs t wch t rwl t dhr t ds t dh valid data open t wp oe v ih v il C C e2g0089-17-41b
10/16 ? semiconductor msm512100/l read modify write cycle ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rwc t rp t ras t crp t rcd t rsh t rwl t cas t crp t csh t ar t cwl t rad t ral t asr t rah t asc t cah row column t awd t rwd t cwd t wp t rcs t ds t dh valid data t cac t aa t rac open t clz oe v ih v il C C t oeh t oed t oea t oez valid data
11/16 ? semiconductor msm512100/l fast page mode read cycle ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rasp t rp t crp t rcd t cas t cp t pc t cas t cp t cas t rsh t crp t ar t asr t rah t asc t cah t asc t cah t asc t cah t ral row column column column t rad t wcr t wcs t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t ds t dh valid data valid data valid data open t dhr t rhcp t wp t cwl t wp t wp t cwl t cwl t rwl note: oe = "h" or "l" fast page mode write cycle (early write) ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" t rasp t rp t csh t crp t rcd t cas t cp t pc t cas t cp t rsh t cas t crp t ar t asr t rah t asc t cah t asc t cah t ral t asc t cah row column column column t rad t rcs t rch t rcs t rch t rcs t rrh t rch t cac t aa t rac t cac t aa t cpa t cac t aa t cpa valid data valid data valid data t clz t off t clz t off t clz t off t rhcp oe v ih v il C C t oea t oea t oea t oez t oez t oez
12/16 ? semiconductor msm512100/l fast page mode read modify write cycle ras cas address we d out v ih v il C C v ih v il C C v ih v il C C v ih v il C C v oh v ol C C "h" or "l" d in v ih v il e e t rasp t csh t prwc t rcd t cas t cp t cas t rsh t rp t crp t cas t ar t asr t rah t asc t cah t asc t cah t asc t cah t ral row column column column t rwd t rcs t cwd t cwl t cwd t cwl t cwd t cwl t awd t aa t rad t cac t ds t awd t cpa t aa t cac t wp t awd t cpa t aa t cac t wp valid data valid data valid data t rac t clz t dh t clz t dh t clz t dh valid data valid data valid data t cp t rcs t rcs t rhcp t cpwd t cpwd t rwl oe v ih v il C C t oea t oea t oea t wp t ds t ds t oed t oed t oed t oez t oez t oez
13/16 ? semiconductor msm512100/l ras -only refresh cycle cas before ras refresh cycle v ih v il ras cas v ih v il C C C C t crp t rp t ras d out "h" or "l" v oh v ol C C t rpc row v ih v il e e open address t asr t rah t rc note: we , oe = "h" or "l" t off v ih v il ras cas v ih v il C C C C t rp t ras d out "h" or "l" v oh v ol C C t rpc v ih v il C C open we t rc t wrh t wrp t rpc t wrp t cp t csr t chr t off note: oe , address = "h" or "l"
14/16 ? semiconductor msm512100/l hidden refresh read cycle hidden refresh write cycle t asr row column v ih v il ras address cas v ih v il v ih v il C C C C C C t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ar t ral t chr t ras t wrh t wrp we d in v ih v il v ih v il C C C C d out "h" or "l" v oh v ol e e valid data t ds t dh t rwl t wp t dhr t wch t wcs t wcr open oe v ih v il C C t asr row column v ih v il ras address we cas v ih v il v ih v il v ih v il C C C C C C C C t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ar t ral d out "h" or "l" v oh v ol e e t rrh t rcs valid data t rac t aa t off t clz t chr t ras t wrh t wrp t cac oe v ih v il C C t roh t oea t oez
15/16 ? semiconductor msm512100/l test mode initiate cycle v ih v il ras cas v ih v il C C C C t ras d out "h" or "l" v oh v ol C C v ih v il C C open we t rc t wth t rpc t wts t cp t csr t chr t off note: oe , address, d in = "h" or "l" t rp
16/16 ? semiconductor msm512100/l (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/20-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish

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